1. Field of the Invention
The present invention relates to an interconnection structure of a semiconductor device having an interconnection provided with a stress concentration portion.
2. Description of the Background Art
In an interconnection structure of a semiconductor device, there is a possibility that a void occurs in an interconnection such as a via or the bottom of a via due to stress migration. Further, the void may cause a disconnection in the interconnection, deteriorating the reliability of the semiconductor device.
To prevent the occurrence of a void, for example, in semiconductor devices described in Japanese Patent Laying-Open Nos. 7-106323 and 9-213800, an insulating film having compressive stress is provided on a side of an interconnection, and an insulating film having tensile stress is provided on the top of the interconnection, with both films provided along a longitudinal direction of the interconnection. These interconnection structures aim at relieving stress in the interconnection and preventing stress migration by mutual buffering action between the tensile stress and the compressive stress.
In addition, in a semiconductor device described in Japanese Patent Laying-Open No. 8-264647, a dummy region which is not used as a component of a circuit is provided in the semiconductor device. The dummy region is provided in proximity to an interconnection, apart from the interconnection. This structure aims at preventing the occurrence of a void in an interconnection structure by causing a void to occur preferentially in the dummy region.
In the semiconductor device described in Japanese Patent Laying-Open No. 7-106323, the insulating film having compressive stress and the insulating film having tensile stress are provided so as to contact the interconnection directly, and stress is relieved by mutual buffering action between the compressive stress and the tensile stress. However, this structure of the semiconductor device is insufficient to prevent a void from occurring locally such as at the bottom of a via. Further, there is a possibility that the insulating film on the side of the interconnection having compressive stress and the insulating film on the top of the interconnection having tensile stress both provided for stress relief would rather promote the formation of a void at the bottom of a via and within the interconnection. For example, when the interconnection is a via, the insulating film on the side of the interconnection having compressive stress applies tensile stress to the via, and thus, a void is apt to be formed at the bottom of the via. Furthermore, in the interconnection within an interconnection layer, since the compressive stress and the tensile stress act on the interconnection, stress concentrates at a weak portion within the interconnection such as a crystal grain boundary or the like, reducing bonding strength in the crystal grain boundary or the like. As a result, it is expected that a void is apt to occur in the crystal grain boundary or the like.
In the semiconductor device described in Japanese Patent Laying-Open No. 9-213800, the insulating film having compressive stress is formed directly on the interconnection, and the insulating film having tensile stress is formed so as to embed the insulating film having compressive stress. In this structure, stress relief is promoted by the action of these two insulating films. As for the insulating film formed directly on the interconnection, its compressive stress in a vertical direction is already relieved during its formation process. Thereby, this insulating film applies tensile stress in a horizontal direction to the interconnection. Further, the embedding insulating film applies tensile stress to the interconnection in vertical and horizontal directions. As a result, large tensile stress is generated within the interconnection, raising the possibility that a void is apt to occur in a crystal grain boundary, in a manner similar to that in the semiconductor device described in Japanese Patent Laying-Open No. 7-106323.
In the semiconductor device described in Japanese Patent Laying-Open No. 8-264647, a structurally weak portion that does not contact the interconnection is formed as a dummy region, and stress is relieved by the dummy region. However, although this structure is effective for stress relief of an interconnection layer as a whole, its effect is insufficient for local stress, because the dummy region is far from the interconnection for which stress should be relieved. Further, since the dummy region is formed within the interconnection layer, it is insufficient to relieve local stress generated at such as the bottom of a via. Furthermore, when a portion between the interconnection and the dummy region is formed of a material such as a low-k material having weak mechanical strength, the dummy region provides the effect of the stress relief to a narrower range, further reducing the effect.